The present invention relates to a floating gate type nonvolatile semiconductor storage device and a write test method for the device.
Conventionally, as a virtual ground type flash memory intended for a high integration density, there can be enumerated the ACT (Asymmetrical Contactless Transistor) type flash memory published in, for example, IEDM Technical Digest, pp. 269-270, 1995 xe2x80x9cA New cell Structure for Subquarter Micron High Density Flash Memoryxe2x80x9d and the Transactions of the Institute of Electronics, Information, and Communication Engineers, ICD 97-21, P37, 1997 xe2x80x9cExamination of ACT Type Flash Memory Sense Systemxe2x80x9d.
This ACT type flash memory utilizes the FN (Fowler-Nordheim) tunneling phenomenon for the write (programming)/erase (erasing) operation and is expected to be used as a data storage type. FIG. 8 is a block diagram of the ACT type flash memory. The ACT type flash memory will be described below with reference to FIG. 8.
In FIG. 8 where the ACT type flash memory cells are arranged in an array form, there are shown a main bit line MBL formed of a metal layer, a sub-bit line SBL formed of a diffusion layer, a word line WL and a select gate signal line SG. The sign ▪ indicates a metal-to-diffusion-layer contact, while the sign xe2x97xaf indicates a diffusion layer connection.
As described above, the ACT type flash memory having the above-mentioned construction utilizes the FN tunneling phenomenon for the write and erase operations, and the array construction is provided in the form of a virtual ground array mechanism where an identical bit line is shared by two memory cells. As described above, in the ACT type flash memory, the number of contacts is reduced by sharing the two bit lines MBL and SBL by the memory cells and forming part of the bit line of a diffusion layer, enabling the achievement of high density integration with a considerably reduced array area.
FIGS. 9 through 11 show the voltage application state during the read operation/write operation/erase operation in the ACT type flash memory. The read operation/write operation/erase operation of the ACT type flash memory will be described in detail below with reference to FIGS. 9 through 11.
As shown in FIG. 9, in the read operation, a voltage of 0 V is applied to adjoining three main bit lines MBL0, MBL1 and MBL2. Two main bit lines MBL3 and MBL4, which are further adjacent to the main bit line MBL2, are precharged with 1 V and thereafter put into a floating state. A voltage of 1 V is applied to one main bit line MBL5 that is further adjacent to the main bit line MBL4. Two main bit lines MBL6 and MBL7, which are further adjacent to the main bit line MBL5, are precharged with 1 V and thereafter put into the floating state. Then, the voltage application pattern of the eight main bit lines MBL of the main bit lines MBL0 through MBL7 will be repeated subsequent to the main bit line MBL8.
In the above case, a potential difference of 1 V is generated between the source and the drain of ACT type flash memory cells 1 and 1 enclosed by the sign ◯ in FIG. 9. Therefore, if the threshold voltage of the ACT type flash memory cells 1 and 1 is lower than the voltage (3 V) of the word line WL0, then a cell current flows, as a consequence of which the drain voltage is lowered. If the threshold voltage of the ACT type flash memory cells 1 and 1 is higher than the voltage (3 V) of the word line WL0, then no cell current flows, as a consequence of which the drain voltage is not lowered. Accordingly, by sensing the difference in the drain voltage by means of a sense amplifier (not shown) via the main bit lines MBL3 and MBL7 with a voltage of 3 V applied to the select gate signal line SG, the information written in the ACT type flash memory cells 1 and 1 is read.
In the write operation, as shown in FIG. 10, a high voltage of 5 V is applied to the n+ side of the sub bit lines (diffusion bit lines) SBL2 and SBL5 of the ACT type flash memory cells 2 and 2 to undergo the write operation in a state in which a negative voltage of xe2x88x928 V is applied to the word line WL0. In the above case, electrons are to be extracted from the floating gates of the ACT type flash memory cells 2 and 2 toward the sub bit lines SBL2 and SBL5 by the FN tunneling phenomenon, as a consequence of which the threshold voltage of the ACT type flash memory cells 2 and 2 is lowered. In general, the threshold voltage of the ACT type flash memory cells 2 and 2 is controlled to about 1 V to 2 V by the write operation.
In the erase operation, as shown in FIG. 11, a voltage of xe2x88x928 V is applied to the sub-bit line SBL in a state in which a high voltage of 10 V is applied to the word lines WL0 through WL31 inside one block to undergo the erase operation demarcated by the select gate signal line SG, and a voltage of xe2x88x928 V is applied to the substrate of the ACT type flash memory cell. In this case, electrons are to be injected from the substrate (channel region) of each ACT type flash memory cell inside one block to undergo the erase operation toward the floating gate by the FN tunneling phenomenon, as a consequence of which the threshold voltage of each ACT type flash memory cell is raised. In general, the threshold voltage of each ACT type flash memory cell is controlled to about 4 V to 6 V by the erase operation.
In the case of FIG. 11, a voltage of 0 V is applied to the select gate signal lines SG0 and SG0, and a voltage of xe2x88x928 V is applied to the select gate signal lines SG1 and SG1, consequently turning on select transistors 3 and 4 whose gates are connected to the select gate signal lines SG0 and SG0. Therefore, a block 0 is selected, and all the ACT type flash memory cells inside the block 0 are erased in a batch. In the above case, the sources and the drains of all the ACT type flash memory cells in the non-selected state, which are put into a high impedance state, are not erased.
As the row decoder circuit of the present ACT type flash memory, there is the following one as shown in FIG. 12. This row decoder circuit 11 is constructed roughly of a driver section 12 for outputting various voltages to the word line WL, a control voltage circuit section 13, a selecting voltage circuit section 14, a non-selecting voltage circuit section 15, a predecoder section 16 and a block decoder section 17.
FIG. 13 shows a circuit diagram of a control voltage circuit 0 that constitutes the control voltage circuit section 13. This control voltage circuit is a circuit for outputting a control signal for turning on and off a P-channel MOS (Metal Oxide Semiconductor) transistor and an N-channel MOS transistor that constitute the driver section 12 of the row decoder 11. Then, output signals hrda0 and hrdab0 are generated by inputting an input signal pre0 (an output signal of a predecoder 0). The input signals other than the input signal pre0 and the power source are common to each control voltage circuit.
FIG. 14 shows a circuit diagram of a selecting voltage circuit 0 that constitutes the selecting voltage circuit section 14. This selected voltage circuit outputs an application voltage to be applied to the selected word line WL via the driver section 12. Then, an output signal hhvx0 is generated by inputting an input signal se10 (an output signal of a block decoder 0). The input signals other than the input signal se10 and the power source are common to each selecting voltage circuit.
FIG. 15 shows a circuit diagram of the non-selecting voltage circuit 0 that constitutes the non-selecting voltage circuit section 15. This non-selected voltage circuit outputs an application voltage to be applied to the non-selected word line WL via the driver section 12. Then, an output signal hnn0 is generated by inputting an input signal se10 (the output signal of the block decoder 0). The input signals other than the input signal se10 and the power source are common to each non-selecting voltage circuit.
FIG. 16 shows a circuit diagram of the predecoder 0 that constitutes the predecoder section 16. FIG. 17 shows a circuit diagram of the block decoder 0 that constitutes the block decoder section 17.
A word line decoding method during the write operation will be described below with reference to FIG. 12. First of all, one block (including 32 word lines WL) is selected from 512 blocks by address signals a5 through a13. Then, the selected block of the driver section 12 is supplied with a write voltage hhvx by the selecting voltage circuit of the selecting voltage circuit section 14 and a voltage of 0 V by the non-selecting voltage circuit of the non-selecting voltage circuit section 15. In contrast to this, the non-selected block of the driver section 12 is supplied with a voltage of 0 V by the selecting voltage circuit of the selecting voltage circuit section 14 and the non-selecting voltage circuit of the non-selecting voltage circuit section 15.
Then, a write voltage is applied only to one word line WL among the 32 word lines WL of the selected block by select signals hrda and hrdab from one control voltage circuit of the control voltage circuit section 13 selected by decoding the address signals a0 through a4 by the predecoder 16. On the other hand, the voltage of 0 V supplied by the non-selecting voltage circuit of the non-selecting voltage circuit section 15 is applied to the remaining word lines WL of the same selected block.
The voltage of 0 V is supplied by the selecting voltage circuit and the non-selecting voltage circuit regardless of the selection/non-selection of the predecoder of the predecoder section 16, and therefore, the voltage of 0 V is to be applied to all the word lines WL.
There are the methods disclosed in Japanese Patent Laid-Open Publication No. HEI 11-224492 and Japanese Patent Laid-Open Publication No. HEI 11-162199 as a test time reducing method for the aforementioned floating gate type nonvolatile semiconductor storage device. According to the former method, by simultaneously selecting a plurality of blocks, the data of the memory cells inside the plurality of blocks are simultaneously subjected to the erase, write and test operations. According to the latter method, a plurality of word lines is enabled by a group of signals for simultaneously driving 2n (n: positive integer) word lines.
However, the write test methods of the aforementioned conventional floating gate type nonvolatile semiconductor storage device have the following problems. That is, according to the ACT type flash memory as shown in FIG. 8, if a memory cell whose threshold voltage is negative (Vt less than 0 V) exists in the selected block as shown in FIG. 18, then the memory cell M0 is to be turned on even when the word line WL0 has a voltage of 0 V. Therefore, it is impossible to measure the threshold voltage of memory cells M1 through M63 that share the sub-bit lines SBL1 and SBL2 with the memory cell M0.
The above matter will be described in more detail below. Reference is first made to the write operation during the write test. It is herein assumed that the memory cell M0 is selected and subjected to the write operation. A voltage of xe2x80x9cHxe2x80x9d level (5 V, for example) is applied to the select gate signal lines SG0 and SG0 to turn on select transistors 21 and 22. Then, a negative high voltage (xe2x88x928 V, for example) is applied to the word line WL0 to which the control gate of the memory cell M0 is connected. A positive voltage (5 V, for example) is applied to the main bit line MBL2 connected to the drain side, and the main bit line MBL1 connected to the source side is put into the floating state (high impedance state).
Further, the main bit line MBL connected to the drain side of other non-selected memory cells M is put in the floating state. The substrate (or p-well) is set to a reference voltage (0 V, for example). It is to be noted that a voltage of 0 V is applied to the word lines WL1 through WL63 connected to the control gates of the non-selected memory cells M.
With this arrangement, the FN tunneling phenomenon occurs between the drain side and the floating gate of the memory cell M0 to undergo the write operation, extracting electrons from the floating gate to the drain side via the tunnel oxide film, and consequently the threshold voltage of the memory cell M0 is lowered. The memory cell M0 is thus put into the write state (in which the threshold voltage becomes 2 V or higher). The write is executed by successively executing the aforementioned write operation in the memory cells M.
Subsequently, when executing the test, the read operation is executed after the aforementioned write operation is executed, and the threshold voltage of the memory cell M0 that has undergone the write operation is measured. If the threshold voltage is not lower than a specified voltage, then the write operation is further executed in the memory cell M0. However, depending on the memory cell M, there is a certain cell whose threshold voltage is very rapidly lowered due to characteristic variations. Therefore, it is sometimes the case where the threshold voltage of the memory cell M that has already put in the write state is 0 V or lower when measuring the threshold voltage.
Moreover, since the threshold voltage of the memory cell M has been not lower than a specified voltage value when measuring the threshold voltage, it is sometimes the case where the threshold voltage of the memory cell M might disadvantageously become 0 V or lower when the write operation is executed again.
Particularly, when the operating voltage of the nonvolatile semiconductor storage device is lowered (for example, the power voltage is 3 V or 1.8 V), the threshold voltage in the write state is required to be lowered. Therefore, the aforementioned situation, which has not occurred up to now, emerges as a problem.
That is, in the case where the threshold voltage of the memory cell M0 becomes 0 V or lower as described above, the following troubles occur when testing the memory cells M other than the memory cell M0. The test operation (read operation) of the memory cells M will be described below. In this case, it is assumed that the memory cell M1 is selected and subjected to the test in FIG. 18.
A voltage of xe2x80x9cH level (3 V, for example)xe2x80x9d is applied to the select gate signal lines SG0 and SG0 to turn on the select transistors 21 and 22. Then, a voltage of 3 V is applied to the word line WL1 to which the control gate of the memory cell M1 is connected. On the other hand, a voltage of 0 V is applied to the non-selected word lines WL0 and WL2 through WL63. Further, a reference voltage (0 V, for example) is applied to the main bit line MBL1 connected to the source side of the memory cell M1, and a precharge voltage of 1 V is applied to the main bit line MBL2 connected to the drain side. The substrate (or p-well) is set to a reference voltage (0 V, for example).
With this arrangement, when the memory cell M1 to be read is in the erase state, no cell current flows since the threshold voltage is not lower than 4 V. Therefore, the voltage of 1 V precharged by the main bit line MBL2 is maintained. When the memory cell M1 is in the write state, a cell current flows since the threshold voltage is not higher than 2 V. Consequently, the voltage of 1 V precharged by the main bit line MBL2 is lowered to a voltage of 0 V. Then, by sensing this precharge voltage by means of the sense amplifier (not shown) connected to the end of the main bit line MBL, the state of the memory cell M1 is determined.
Assuming that the memory cell M0 is in an excessive write state (in which the threshold voltage is negative: overprogramed state) as described above, then a cell current is to flow through the memory cell M0 when a voltage of 0 V is applied to put the word line WL0 into the non-selected state. Therefore, if the transition of the precharge voltage is determined by the main bit line MBL2, then the precharge voltage of the main bit line MBL2 is lowered regardless of the state of the memory cell M1 subjected to the test. Therefore, the state of the memory cell M1 cannot correctly be determined. The same phenomenon also occurs in the memory cells M2 through M63 of which the drain side is connected to the main bit line MBL2.
That is, according to the Japanese Patent Laid-Open Publication No. HEI 11-224492, the test operation (read operation) is simultaneously executed inside the arbitrary block. Therefore, when at least one memory cell whose threshold voltage has become negative exists, the threshold voltage of the memory cells M1 through M63 that share the sub-bit lines SBL1 and SBL2 with the memory cell M0 cannot be measured as described above, and this leads to the problem that the write test is consequently not normally executed.
According to the Japanese Patent Laid-Open Publication No. HEI 11-162199, the test operation (read operation) is executed by simultaneously selecting 2n word lines. Therefore, in the case where a plurality of word lines are selected inside an identical block, the test cannot normally be executed likewise when at least one memory cell whose threshold voltage has become negative exists.
Furthermore, a xe2x80x9clogic gatexe2x80x9d is added so as to enable the switching between the simultaneous selection of all the word lines and the stripe pattern selection for simultaneously selecting the odd-number or even-number word lines in a test mode. However, because of the OR gate, the word line to which the test signal is inputted is to be selected, and a plurality of word lines are selected inside an identical block. Therefore, in the case where the word lines having only the memory cells in which the write operation has normally been executed and the word lines including the memory cells in which the write operation has not normally been executed are existing in mixture inside an identical block, the write voltage is to be applied again to the memory cells in which the write operation has normally been executed when the write operation is executed again in the memory cell in which the write operation is not normally executed. As a result, there is the problem that the unnecessary write voltage is applied to the memory cell in which the write operation has normally been executed.
Accordingly, the object of the present invention is to provide a nonvolatile semiconductor storage device capable of executing the write test so that a plurality of word lines are not selected inside an identical block and a test method for the device.
In order to achieve the above object, there is provided a nonvolatile semiconductor storage device including floating gate field-effect transistors that are provided with a control gate, a floating gate, a drain and a source, able to electrically write and erase information and arranged in a matrix form on a substrate or a well and including a plurality of row lines connected to the control gates of the floating gate field-effect transistors arranged in a direction of row, the device comprising:
a block switching means for dividing the row lines into blocks every several lines and connecting a plurality of first column lines connected to the drains and sources of the floating gate field-effect transistors arranged in a direction of column in each block to a second column line arranged commonly to all the blocks;
block selecting means for selecting any one of the plurality of blocks;
a row line selecting means for selecting any one of the plurality of row lines inside the selected block; and
an all blocks selecting means, provided for the block selecting means, for selecting all the blocks on the basis of a first control signal.
According to the above construction, in the write operation during the test, all the blocks are selected by the all blocks selecting means of the block selecting means and one row line in every block is selected by the row line selecting means, simultaneously applying the write voltage to the row lines selected one after another from all the blocks. Then, in measuring the threshold voltage, the block switching means is turned off to electrically separate the non-measured blocks from the measured block. Therefore, even if a floating gate field-effect transistor in which the threshold voltage is negative exists in a certain block, the bad influence exerted by the floating gate field-effect transistor when measuring the floating gate field-effect transistors of other blocks is eliminated.
In one embodiment of the present invention, the nonvolatile semiconductor storage device comprises:
a selection preventing means, provided for the block selecting means, for preventing a subsequent selecting operation of a block currently selected by an address signal on the basis of a second control signal.
According to the above construction, when the threshold voltages of all the floating gate field-effect transistors connected to the selected row of the currently selected block by the address signal are normal in measuring the threshold voltage during the test, the subsequent selecting operation to the selected block is prevented by the selection preventing means. Thus, an excessive stress is prevented from being applied to the floating gate field-effect transistors, which exist in the block and in which the threshold voltages are normal, is prevented, when the write operation is executed again in the floating gate field-effect transistors of other blocks.
In one embodiment of the present invention, the nonvolatile semiconductor storage device comprises:
a resetting means, provided for the block selecting means, for setting the state of selection by the all blocks selecting means back into an initial state on the basis of a third control signal.
According to the above construction, when the write, threshold voltage measurement and rewrite operations of the floating gate field-effect transistors connected to the row lines selected one after another from all the blocks are ended, the selective state set by the all blocks selecting means is set back to the initial state by the resetting means. Thus, the block selection when, for example, erasing the floating gate field-effect transistors that have undergone the write test is accurately executed.
Also, there is provided a method for testing a nonvolatile semiconductor storage device including floating gate field-effect transistors that are provided with a control gate, a floating gate, a drain and a source, able to electrically write and erase information and arranged in a matrix form on a substrate or a well, including a plurality of row lines connected to the control gates of the floating gate field-effect transistors arranged in a direction of row and including a block switching means for connecting a plurality of first column lines connected to the drains and sources of the floating gate field-effect transistors arranged in a direction of column inside each of blocks constructed by dividing the row lines every several lines to a second column line arranged commonly to all the blocks, the method comprising the steps of:
selecting one after another the row lines from all the blocks divided by the block switching means and simultaneously applying a write voltage to the selected row lines during a write test.
According to the above construction, during the write test, the write voltage is simultaneously applied to the row lines selected one after another from all the blocks. Then, in measuring the threshold voltage, the block switching means is turned off to electrically separate the non-measured block from the measured block. Therefore, even if a floating gate field-effect transistor in which the threshold voltage is negative exists in a certain block, the bad influence exerted by the floating gate field-effect transistor when measuring the floating gate field-effect transistors of other blocks is eliminated.
Furthermore, the erase voltage is applied only to the row line relevant to the memory cell that is required to be subjected to the erase operation, and therefore, the threshold voltage can be prevented from being raised by the repetitive application of the erase voltage to the memory cells every erase operation. This may produce remarkable effects on the memory cells that will be manufactured by finer processing in the future.
Furthermore, all the memory cells are erased in a batch, and therefore, the erase time can be shortened.
Also, there is provided a method for testing a nonvolatile semiconductor storage device including floating gate field-effect transistors that are provided with a control gate, a floating gate, a drain and a source, able to electrically write and erase information and arranged in a matrix form on a substrate or a well, including a plurality of row lines connected to the control gates of the floating gate field-effect transistors arranged in a direction of row and including a block switching means for connecting a plurality of first column lines connected to the drains and sources of the floating gate field-effect transistors arranged in a direction of column inside each of blocks constructed by dividing the row lines every several lines to a second column line arranged commonly to all the blocks, the method comprising the steps of:
selecting one after another the row lines from an arbitrary block of the blocks divided by the block switching means and simultaneously applying a write voltage to the selected row line during a write test.
According to the above construction, during the write test, the write voltage is simultaneously applied to the row lines selected one after another from arbitrary blocks. Then, in measuring the threshold voltage, the block switching means is turned off to electrically separate the non-measured block from the measured block. Therefore, even if a floating gate field-effect transistor in which the threshold voltage is negative exists in a certain block, the bad influence exerted by the floating gate field-effect transistor when measuring the floating gate field-effect transistors of other blocks is eliminated.
In one embodiment of the present invention, the row line connected to only the floating gate field-effect transistor in which the write operation has normally been executed is not selected when the write operation is executed again in the floating gate field-effect transistor in which the write operation has not normally been executed.
According to the above construction, the row line connected to only the floating gate field-effect transistor in which the write operation has normally been executed is not selected when the write operation is executed again in the floating gate field-effect transistor in which the write operation has not normally been executed. Thus, the floating gate field-effect transistors in which the threshold voltages are normal are prevented from being applied by an excessive stress when the write operation is executed again.
In one embodiment of the present invention, an erase voltage is applied to the selected row line of each block after write, threshold voltage measurement and rewrite operations of all the floating gate field-effect transistors connected to one row line selected from each block are ended.
According to the above construction, the erase voltage is applied to the row line in which the write, threshold voltage measurement and rewrite operations have been ended. Thus, the bad influence exerted by the floating gate field-effect transistor having undergone the write test on the other floating gate field-effect transistor undergoing the subsequent write test is prevented.
In one embodiment of the present invention, an erase voltage is applied to all the row lines of all the blocks after write, threshold voltage measurement and rewrite operations of all the floating gate field-effect transistors connected to one row line selected from each block are ended.
According to the above construction, every time the write, threshold voltage measurement and rewrite operations of the selected row line are ended, the erase voltage is applied to all the row lines of all the blocks. Thus, the bad influence exerted by the floating gate field-effect transistor having undergone the write test on the other floating gate field-effect transistor undergoing the subsequent write test is reliably prevented.